1. Field of the Disclosure
The invention generally relates to a semiconductor device and, more particularly, to an isolation structure in a memory device and a method for fabricating the same.
2. Brief Description of Related Technology
As an integration degree of semiconductor memory devices is raised, a design rule of circuit patterns is also rapidly reduced. For example, as a design rule of a Dynamic Random Access Memory (DRAM) device is reduced to less than 50 nm, finer patterns must be formed. With the reduction in a design rule, a superior gap filling property is required in a process of forming an isolation structure. Since an aspect ratio of the trench is sharply increased and the width of the trench is more decreased when the isolation structure is realized in a Shallow Trench Isolation (STI) method, it is required that an insulation material for filling the trench has higher gap filling properties.
As the design rule is rapidly reduced to less than 50 nm, a process of filling the trench by high density plasma (HDP) deposition represents a limitation. Therefore, a method of filling the trench using flowable dielectric that represents higher gap filling properties as compared to HDP oxide has been tried. In this method using the flowable dielectric, the isolation layer is formed to fill the trench by coating an insulation material source in liquid or suspension form, filling the trench using flowability of the liquid source and then curing the coated layer. This coating process can be performed using a spin coater. The insulation layer by this process can be appreciated as a Spin On Dielectric (SOD).
However, when forming the isolation layer using this flowable insulator, deterioration of punchthrough properties in PMOS transistors is observed. The PMOS transistor is mainly formed in a peripheral region of the DRAM device and Hot Electron Induced Punchthrough (HEIP) properties of the PMOS transistor represent rapid deterioration. This is a result of a nitride liner introduced in an interface between the flowable insulation layer and side wall and bottom of the trench.
FIGS. 1 and 2 illustrate the HEIP of a PMOS transistor.
Referring to FIG. 1, an isolation layer 20 that defines an active region 10 in a semiconductor substrate may be formed in a STI structure. At this time, an operation of a gate 30 of the PMOS transistor formed on the active region 10 is affected by effective channel width in the active region 10. This effective channel width depends on the width of the active region 10, but is also affected by distribution of charges trapped in the interface between the active region and the isolation layer 20.
For example, as the design rule rapidly decreases, an electric field between the channels increases, and a relatively large number of hot electrons are generated. These hot electrons (e) penetrate into the isolation layer 20 and are trapped in the interface at the isolation layer 20 side, and P-type carriers such as a hole (+) are trapped in the interface at the opposite active region 10 side by the trapped electrons (e). These P-type carriers actually induce an effect of reducing the effective channel width of the PMOS transistor. By this reduction in the channel width, a threshold voltage (Vt) of the PMOS transistor is rapidly reduced, and off-leakage current is rapidly increased.
Referring to FIG. 2, a triple liner structure of a first silicon oxide layer 21, a silicon nitride layer 23, and a second silicon oxide layer 25 for the improvement of interface properties is introduced between the active region 10 and the isolation layer 20. When considering a potential well according to the liner structure, it can be appreciated that the hot electrons (e) can be trapped in the silicon nitride layer 23. Actually, the hot electrons (e) are trapped in a trap site that is present in the silicon nitride layer 23 and deteriorate the HEIP properties of the PMOS transistor.
This deterioration of the HEIP properties of the PMOS transistor may become more serious when forming the isolation layer 20 with the flowable insulation layer. When forming the flowable insulation layer, extreme stress may be caused between the isolation layer and the liner of the silicon nitride 23 therebelow in the process of curing the liquid insulation material source after coating it. The stress may be caused from contraction of the insulation layer that occurs when curing the flowable insulation layer. This stress causes an effect that increases the electron trap sites in the silicon nitride layer 23, and this may result in the trap of more hot electrons (e) in the interface of the isolation layer 20 as shown in FIG. 1. Therefore, the HEIP properties of the PMOS transistor are deteriorated more seriously.